A semiconductor circuit includes a phase lock loop (PLL) having a voltage controlled oscillator (VCO) to generate a VCO frequency signal. However, process variations of the semiconductor circuit cause changes in the VCO frequency signal at different process corners. An adjustable capacitance circuit in a tank circuit may be used to control the VCO frequency. Because the capacitance varies with the desired VCO frequency, a VCO capacitance switch may be used. The frequency of the phase lock loop may be calibrated to control the VCO capacitance switch.
In one calibration scheme, the calibration of the frequency of the phase lock loop is performed each time a frequency is selected. A varactor control voltage is set to the voltage at one-half of the supply voltage. A digital frequency counter estimates the frequency while sweeping a full range of capacitors. The correct number of capacitors is determined for the estimated frequency closest to the desired frequency. This calibration scheme has a long settling time, and the calibration is done every time that the frequency is changed.
In another calibration scheme, the calibration of the frequency of the phase lock loop is performed for all frequencies after start up and the calibration values are stored in an on-chip static random access memory (SRAM). When the frequency is changed, the corresponding calibration value is read from the SRAM and used to set the capacitance of the tank circuit. This calibration scheme uses a large SRAM area on the semiconductor circuit and has a slow start-up.